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| Communication ICs 4-channel ADPCM transcoder for digital cordless telephone base stations BU8710AKS This is an ADPCM transcoder which conforms to the G.721 standards listed in the 1988 edition of the CCITT recommendations. Simultaneous processing of four encoder and decoder channels is possible, enabling superb affinity with the quadruple TDMA which is a standard for PHS (personal handy phone) systems. In turn, this enables voice processing units for individual base stations in the public telephone network to be configured on single chips. FApplications PHS base stations FFeatures 1) Can be connected to -law and A-law PCM codec through a serial interface. (Both long frames and short frames can be accommodated.) 2) Various functions can be controlled through a CPU interface. 3) An internal power save mode can be controlled separately for individual channels. (Separate encoder and decoder control are possible.) In addition, external pin control enables power consumption to be reduced for the chip as a whole. 4) An internal muting function can be controlled separately for individual channels. (Separate encoder and decoder control are possible.) 5) An internal function silence detection is provided, which can be controlled separately for individual channels. (Applicable only to encoders.) 6) An internal background noise generation function is provided, which can be controlled separately for individual channels. (Applicable only to decoders.) 7) The G.711 (-law or A-law) output level can be attenuated freely on individual channels. 8) An internal 64kbps data through mode is provided, which can be controlled separately for individual channels. 9) Internal 32kbps and 64kbps data loop back modes are provided, which can be controlled separately for individual channels. 10) An internal clock generator circuit is provided. 11) SQFP 80 pin package is used. 99 Communication ICs FBlock diagram BU8710AKS 100 Communication ICs FAbsolute maximum ratings (Ta = 25_C) BU8710AKS FRecommended operating conditions (Ta = 25_C) FPin descriptions 101 Communication ICs BU8710AKS 102 Communication ICs BU8710AKS FElectrical characteristics DC characteristics (unless otherwise noted, Ta = 25_C, VDD = 5.0V) 103 Communication ICs AC characteristics (unless otherwise noted, Ta = 25_C, VDD = 5.0V) BU8710AKS 104 Communication ICs FInput / output signal timing charts BU8710AKS 105 Communication ICs BU8710AKS 106 Communication ICs BU8710AKS 107 Communication ICs BU8710AKS Note: In Figures 2 to 5, when the 64kbps data through mode is set, the normal 4-bit output encoder output is equivalent to the timing of the decoder 8-bit output (corresponding to Figure 5), and the normal 4-bit input decoder input is equivalent to the timing of the encoder 8-bit input (corresponding to Figure 2). Correspondence between encoder and decoder input pins Correspondence between encoder and decoder output pins 108 Communication ICs FControl signal timing charts BU8710AKS 109 Communication ICs BU8710AKS 110 Communication ICs FDescription of functions (1) 4-channel G.721 ADPCM processor This is a 32kbps ADPCM processor which conforms to the G.721 standards listed in the 1988 edition of the CCITT recommendations, and is capable of 4-channel simultaneous processing. Various kinds of control can be carried out through a CPU interface. Calculations on the eight systems listed below can be processed simultaneously. Channel 1-A, encoder Channel 1-B, encoder Channel 2-A, encoder Channel 2-B, encoder Channel 1-A, decoder Channel 1-B, decoder Channel 2-A, decoder Channel 2-B, decoder When Pin / A is HIGH, calculation is carried out in the -law mode, and when LOW, calculation is carried out in the A-law mode. (2) Clock generator circuit This LSI has an internal clock generator circuit which can be connected to a crystal resonator. Setting the PDN pin to LOW stops the clock generator circuit, enabling the line current to be suppressed to a minimum. When signals are input directly from an external generator circuit, the clock should be supplied to the OSCIN pin. BU8710AKS (3) CPU interface The CPU interface data bus allows either 4-bit or an 8-bit parallel data transmission to be selected. When data is written to or read from the internal registers, the user can initiate control over various types of functions provided with this LSI. The following section describes pins relating to the CPU interface. S MC / D G G G Switches between commands and data from the CPU. When reading or writing data via the data bus, this switches between command and register data. When the MC / D pin is HIGH, commands can be written, and when LOW, register data can be read and written. S MH / L G G G Switches between the upper and lower bits of the data from the CPU. When using the 4-bit interface, this switches the upper and lower four bits of the data. When the MH / L pin is HIGH, commands are written, and the upper four bits of the register data can be read and written. When MH / L is LOW, the lower four bits of the register data can be read and written. When using the 8-bit interface, MH / L is left at LOW. S MCS G G G Selects the chip from the CPU. When reading and writing data, the MCS pin is set to the LOW state. S MRD G G G Enables reading from the CPU. Data can be read from the data bus by setting MCS to LOW, MRD to LOW, and MWR to HIGH. S MWR G G G Enables writing from the CPU. Data can be written from the data bus by setting MCS to LOW, MRD to HIGH, and MWR to LOW. S MDAT7 X0 GGG CPU 8-bit data bus. Because there is no internal pull-up or pull-down resistance, processing should be done externally. When using the 4-bit interface, use MDAT3 X 0 on the lower bit side. S MRDRQ GGG Sends a request to the CPU to read data. On channels where silence detection is enabled, if a silence state is detected, MRDRQ goes LOW. 111 Communication ICs 1) CPU interface truth table BU8710AKS 112 Communication ICs BU8710AKS 113 Communication ICs 2) Internal register mapping BU8710AKS S Command No.: 0 (NOP) No processing is carried out with this command. S Command No.: 1 (RESET) Writing "H" to the corresponding internal register initializes the individual encoder and decoder for the channel. The status at this point is the optional reset status noted in the 1988 edition of the CCITT recommendations for the G.721. RESE1A G G Channel 1-A encoder initialized RESE1B G G Channel 1-B encoder initialized RESE2A G G Channel 2-A encoder initialized RESE2B G G Channel 2-B encoder initialized RESD1A G G Channel 1-A decoder initialized RESD1B G G Channel 1-B decoder initialized RESD2A G G Channel 2-A decoder initialized RESD2B G G Channel 2-B decoder initialized 114 Communication ICs S Command No.: 2 (POWER DOWN) Writing "H" to the corresponding internal register sets the power down mode for the individual encoder and decoder for the channel. At this point, the G.721 ADPCM processor simply stops calculation processing. PDNE1A G G G G Channel 1-A encoder in power down mode PDNE1B G G G G Channel 1-B encoder in power down mode PDNE2A G G G G Channel 2-A encoder in power down mode PDNE2B G G G G Channel 2-B encoder in power down mode PDND1A G G G G Channel 1-A decoder in power down mode PDND1B G G G G Channel 1-B decoder in power down mode PDND2A G G G G Channel 2-A decoder in power down mode PDND2B G G G G Channel 2-B decoder in power down mode S Command No.: 3 (MUTE) Writing "H" to the corresponding internal register sets the mute mode for the individual encoder and decoder for the channel. In data through mode and data loop back mode, muting processing is not carried out. MUTE1A G G G G Muting on Channel 1-A encoder MUTE1B G G G G Muting on Channel 1-B encoder MUTE2A G G G G Muting on Channel 2-A encoder MUTE2B G G G G Muting on Channel 2-B encoder MUTD1A G G G G Muting on Channel 1-A decoder MUTD1B G G G G Muting on Channel 1-B decoder MUTD2A G G G G Muting on Channel 2-A decoder MUTD2B G G G G Muting on Channel 2-B decoder S Command No.: 4 (BACK NOISE) Writing "H" to the corresponding internal register generates background noise from the decoder output of each individual channel. The noise output level can be controlled to any level using registers BNLVL2 to 0 (command no.: 5). In data through mode and data loop back mode, background noise is not generated. BNSD1A G G G G Background noise generated for Channel 1-A decoder BNSD1B G G G G Background noise generated for Channel 1-B decoder BNSD2A G G G G Background noise generated for Channel 2-A decoder BNSD2B G G G G Background noise generated for Channel 2-B decoder BU8710AKS S Command No.: 5 (NOISE LEVEL) This sets the output level for the background noise generated by the register BNSxxx (command no.: 4) setting. The noise output levels in the table below are the values calculated on a logic basis. S Command No.: 6 (VDET ENABLE) Writing "H" to the corresponding internal register initiates silence detection for the encoder input of each individual channel. The standard level and time for the silence detection is supplied by registers VDLV12 X 00 (command nos.: 8 and 9) and registers VDTIM5 X 0 (command no.: A). The results of the silence detection can be checked by means of a flag using register VDFxxx (command no.: 7). In data through mode and data loop back mode, silence detection is not carried out. VDEE1A G G G G Silence detection enabled for Channel 1-A encoder VDEE1B G G G G Silence detection enabled for Channel 1-B encoder VDEE2A G G G G Silence detection enabled for Channel 2-A encoder VDEE2B G G G G Silence detection enabled for Channel 2-B encoder If any of the encoders on channels for which silence detection is enabled is actually in the silence detection enabled state (in register VDFxxx, one or more bits are HIGH), the MRDRQ pin goes LOW. If silence detection is not in effect on any of the encoders on channels for which it is enabled (all bits of register VDFxxx are LOW), the MRDRQ pin is HIGH. 115 Communication ICs S Command No.: 7 (VDET FLAG) For channels on which encoder silence detection is enabled by register VDFxxx (command no. : 6), a flag can be read out which indicates a silent status (HIGH). This flag can only be read and cannot be written. VDFE1A G G G G Silence detection flag for Channel 1-A encoder VDFE1B G G G G Silence detection flag for Channel 1-B encoder VDFE2A G G G G Silence detection flag for Channel 2-A encoder VDFE2B G G G G Silence detection flag for Channel 2-B encoder S Command No.: 8 (VDET L-LEVEL) S Command No.: 9 (VDET U-LEVEL) When encoder silence detection is being carried out, these set the reference level on which judgments are based. This set value is supplied as a 13-bit linear absolute value. VDLV12 X 00 G G G G Sets reference level on which encoder silence detection judgments are based. S Command No.: A (VDET TIME) When encoder silence detection is carried out, this sets the time interval for judgment. The set value issupplied in 6 bits. VDTIM5 X 0 G G G G Sets the time for judgment of encoder silence. The time is calculated using the equation below. [Judgment time] = VDTIM 8ms Ex.: If VDTIM = 110000 (binary), the judgment time will be 48 8ms = 384ms S Command No.: B (OUT LEVEL) By writing the desired value to the corresponding internal register, the decoder output level for each individual channel can be attenuated to the desired level. In data through mode or data loop back mode, the output level cannot be controlled. OLV1A1, OLV1A0 G G G G Output level control of Channel 1-A decoder OLV1B1, OLV1B0 G G G G Output level control of Channel 1-B decoder OLV2A1, OLV2A0 G G G G Output level control of Channel 2-A decoder OLV2B1, OLV2B0 G G G G Output level control of Channel 2-B decoder Two bits of control data are assigned to each channel,enabling adjustment in a total of four stages. The relationship between the set value and the output level is shown BU8710AKS in the table below. The output levels noted here are recorded using the value prior to attenuation (0dB) as a reference. S Command No.: C (THRU MODE) Writing "H" to the corresponding internal register sets the 64kbps data through mode for the individual encoders and decoders of the various channels. THRE1A G G G G 64 kbps data through mode for Channel 1-A encoder THRE1B G G G G 64 kbps data through mode for Channel 1-B encoder THRE2A G G G G 64 kbps data through mode for Channel 2-A encoder THRE2B G G G G 64 kbps data through mode for Channel 2-B encoder THRD1A G G G G 64 kbps data through mode for Channel 1-A decoder THRD1B G G G G 64 kbps data through mode for Channel 1-B decoder THRD2A G G G G 64 kbps data through mode for Channel 2-A decoder THRD2B G G G G 64 kbps data through mode for Channel 2-B decoder 116 Communication ICs S Command No. : D (LOOP BACK) Writing "H" to the corresponding internal register sets the 64 kbps data loop back mode for the encoder input ! decoder output and the 32 kbps data loop back mode for the decoder input ! encoder output. LPBK1A G G G G Loop back mode for Channel 1-A encoder/ decoder LPBK1B G G G G Loop back mode for Channel 1-B encoder/ decoder LPBK2A G G G G Loop back mode for Channel 2-A encoder/ decoder LPBK2B G G G G Loop back mode for Channel 2-B encoder/ decoder BU8710AKS S Command No.: E (SERIAL MODE) This is used to select the timing for the input and output serial interfaces of the encoder and decoder. When register SIFMOD is LOW, the normal operation mode is effective (short frame or long frame), and when register SIFMOD is HIGH, the synchronous mode is effective. This setting is applied to all channels, and cannot be specified separately for individual channels. SIFMOD G G G G This switches the serial interface mode. If a CPU interface is not being used, the mode can be switched as shown in the truth table below, based on the logic level of the CPU interface pin. (4) Serial interface This is the serial interface which is used to input and output data to and from the 4-channel encoders and decoders. It accommodates all interfaces : the long frame in normal mode, the short frame in normal mode, and the synchronous mode. Interfaces and signal names In the 64kbps through mode (command no.: C) and the 64kbps / 32kbps data loop back mode (command no.: D), some functions cannot be used. Please refer to the table below. 117 Communication ICs The "Enable" and "Data" items are input and output individually for each channel. Clocks are input individually, with one clock being input for two channels. With serial interfaces, the following three types of timing are available. Timings and their features BU8710AKS Generally speaking, there are two types of timing, for normal mode and for synchronous mode. Normal mode timing is further subdivided into long frame and short frame timing. S Normal mode This is the mode in which either the long frame or short frame can be used. Switching between the long and short frame is done automatically, based on the pulse width of the Enable signal. S Synchronous mode This is a special timing mode. In this mode, data is input and output in sequential order, immediately following the rising edge of the Enable signal, regardless of the pulse width of the Enable signal. 118 Communication ICs 1) Timings for the various modes Figures 17 to 20 show the relations between the serial clock, Enable signal, and data for the various encoder and decoder input and output, in the normal mode and the synchronous mode. BU8710AKS 119 Communication ICs BU8710AKS 120 Communication ICs 2) Relation between clock frequency and data word length Serial data is interfaced in two lengths, 8 bits and 4 bits. For 8-bit data, the transmission speed is 64kbps, and for 4-bit data, the speed is 32kbps. 1. For 64 kbps transmission The clock frequency is set within a range of 64kHz to 8MHz. This transmission speed is applicable in the following cases. S For encoder input and decoder output when normal ADPCM calculation is being carried out. S For encoder and decoder input and output in the data through mode. S For encoder input and decoder output in the data loop back mode. 3) Output delays in relation to input After data is input, it takes a certain amount of time for the data to undergo ADPCM calculation before being output. This section explains delays in data output in relation to data input. First, we will look at the relationship between the timing at which serial data is input from and output to an external source, and internal operation. In Figures 21 to 24, the timings for items 1 to 3 and 7 to 9 are indicated as seen from the pins, while items 4 to 6 show internal signal states. The items are explained below, in numeric order. 1. An 8-bit or 4-bit data row is input serially based on the input clock 1 , Input Enable signal 2 , and input data 3 . Figures 21 to 24 show the states for the normal mode only. The timing for the synchronous mode is equivalent to that for the long frame in the normal mode. 2. Immediately after the 8-bit or 4-bit data has been input serially at step 1 , the calculation start pulse 4 is generated. Also, at this point, the data which is the target of the calculation 5 , which has been converted from serial to parallel data, is prepared as parallel 8-bit or 4-bit data. BU8710AKS 2. For 32 kbps transmission The clock frequency is set within a range of 32kHz to 8MHz. This transmission speed is applicable in the following cases. S For decoder input and encoder output when normal ADPCM calculation is being carried out. S For decoder input and encoder output in the data loop back mode. 3. The calculation is carried out on the target data. Calculation is completed before the next calculation start pulse 4 is received, and the resulting data 6 is updated by the calculation start pulse 4 . In the data through and data loop back modes as well, the ADPCM calculation processing is omitted, but the timing at which the resulting data 6 is updated remains the same. 4. The data resulting from the calculation 6 is latched in order to be converted from parallel to serial data. With a short frame in the normal mode, this is done following one cycle after the rising edge of the Output Enable signal 8 , at the rising edge of the output clock 7 . With a short frame in the normal mode, and in the synchronous mode, this is done at the rising edge of the Output Enable signal. In addition, the 8-bit or 4-bit data is output serially based on the output clock, the Output Enable signal 8 , and the Output Data signal 9 . [Supplementary information for Figures 21 X 24] S SDi (k) G G G G Serial input data targeted for calculation S PDi (k) G G G G Parallel input data targeted for calculation S PDO (k) G G G G Parallel output data resulting from calculation S SDo (k) G G G G Serial output data resulting from calculation 121 Communication ICs 4) Normal ADPCM calculation for the encoder Figure 21 shows the data delays that take place with normal ADPCM calculation for the encoder. BU8710AKS As shown in Figure 21, if the input clock exceeds 64kHz and the output clock exceeds 32kHz, and the Input Enable and Output Enable are in the same phase, a delay equal to two data samplings will occur. Delays occurring under other conditions can also be determined based on Figure 21. 122 Communication ICs 5) Normal ADPCM calculation for the decoder Figure 22 shows the data delays that take place with normal ADPCM calculation for the decoder. BU8710AKS As shown in Figure 22, if the input clock exceeds 32kHz and the output clock exceeds 64kHz, and the Input Enable and Output Enable are in the same phase, a delay equal to two data samplings will occur. Delays occurring under other conditions can also be determined based on Figure 22. 123 Communication ICs 6) Data through mode and loop back mode Figure 23 shows data delays in the 64kbps data through mode, for the encoder and decoder. The figure also shows data delays in the 64kbps data loop back mode, for encoder input and decoder output. BU8710AKS As shown in Figure 23, if the input / output clock exceeds 64 kHz and the Input Enable and Output Enable are in the same phase, a delay equal to two data samplings will occur. Delays occurring under other conditions can also be determined based on Figure 23. 124 Communication ICs Figure 24 shows data delays in the 32kbps data loop back mode, for the decoder input and encoder output. BU8710AKS As shown in Figure 24, if the input / output clock exceeds 32kHz and the Input Enable and Output Enable are in the same phase, a delay equal to two data samplings will occur. Delays occurring under other conditions can also be determined based on Figure 24. 125 Communication ICs (5) Silence detection method Silence states can be judged if all of the conditions listed below have been met. The results of the silence detection are stored in register VDFxxx. Condition 1 Must be in Silence Detection Enable state (register VDExxx = HIGH). Condition 2 Must be within the specified reference level (set using registers VDLV12 to 00). The reference level is applied as an absolute value, so it will be within a range of VDLV to - VDLV. Condition 3 Conditions 1 and 2 must be met continuously for more than a given period of time (set using registers VDTIM5 to 0). Figure 25 shows silence detection conditions. BU8710AKS 126 Communication ICs FApplication BU8710AKS 127 Communication ICs FBoard component layout BU8710AKS Connector pin correspondence table 128 Communication ICs Items relating to switches and LEDs BU8710AKS 129 Communication ICs (1) Preparing peripheral circuits 1 Processing a 50-pin connector All of the pins in the serial interface (pin numbers 1 to 47, excluding the GND pin) are pulled up on the board, so only those pins which will actually be used should be connected to the desired signals. If the reset pin (pin 49) is not being used, it should be processed to the GND pin. 2 Processing the power supply A power supply of 5 V should be supplied from POWER on the board. (2) Operation procedure [Basic operation] 1 Using SW17, set the master clock frequency. 2 Using SW18, set the G.711 format. 3 Using SW16, turn off the power save mode. 4 Press the reset switch to initialize the LSI. At this point, normal voice transmission can be carried out through the serial interface. FExternal dimensions (Units: mm) BU8710AKS [Writing data to internal registers] 1 Using SW1 X SW4, set the command number. 2 Using SW5 X SW12, set the data to be written. 3 Press SW13 to write the data to the internal register. 4 The data is read automatically immediately after it has been written, and is displayed by LED1 X LED8. Check to make sure the data has been written correctly. [Reading data from internal registers] 1 Using SW1 X SW4, set the command number. 2 Turn on SW14 to read the data for the command number set using SW1 X SW4 in serial time. The results are displayed by LED1 X LED8. If the settings for SW1 X SW4 have been changed, the results displayed will change accordingly. Data can also be written while other data is being read. 130 |
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